1. Field of the Invention
The present invention relates to an LSI (Large-Scale Integrated) circuit designing system, an antenna damage preventing method, and an antenna damage prevention controlling program used in the LSI circuit designing system and more particularly to the LSI circuit designing system suitably used in the LSI circuit designing system capable of preventing antenna damage, which is caused by a wiring erroneously operating as an antenna in some cases formed during processes of manufacturing a semiconductor integrated circuit such as the LSI, occurring in a gate insulating film (for example, a gate oxide film of a MOS [Metal Oxide Semiconductor]) transistor making up a MIS (Metal Insulator Semiconductor) transistor mounted internally in the LSI, to the antenna damage preventing method and to the antenna damage prevention controlling program to be used for the LSI circuit designing system.
The present application claims priorities of Japanese Patent Application Nos. 2006-101180 filed on Mar. 31, 2006 and 2007-052095 filed on Mar. 1, 2007, which are hereby incorporated by reference.
2. Description of the Related Art
Conventionally, in wiring metal layer processing at a time of manufacturing semiconductor integrated circuits such as LSIs, there are some cases in which a wiring segment, due to the reason that it erroneously operates as an antenna, absorbs electrostatic charges during the processing of plasma etching, which is then discharged, when the charges exceed a specified level, through a gate electrode of each of MOS transistors connected to the above wiring segment and, as a result, the electrostatic charges cause damage to a gate oxide film of each of the MOS transistors. For example, in the case of wiring configurations as shown in FIG. 14, in the process of forming the wiring layer (Layer M1), a wiring segment (Seg. 1, 1), due to its connection to a gate pin (Gate) through a via (VIA), is a metal that may cause gate damage (hereinafter the metal segment causing gate damage being referred to as an “antenna object”) and a wiring segment (Seg. 1, 2), owing to non-connection to a gate pin, is not a metal that may cause gate damage (hereinafter the metal segment causing no gate damage being referred to as an “antenna non-object”).
Similarly, in the process of forming a Layer M2, a wiring Seg. 2, 1 is an antenna object and a wiring Seg. 2, 2 is an antenna non-object. In the process of forming a Layer M3, a wiring Seg. 3, 1 is an antenna object and a Seg. 3, 2 is an antenna non-object. In the LSI circuit designing system, by using an antenna error judging calculating formula shown in FIG. 14, it is verified that a value on the right side of the equation does not exceed a value on the left side of the equation for every wiring net in each wiring layer (Layer) and a wiring segment causing an antenna error is detected and recognized and an antenna error is corrected. As a reference value on the left side of the equation, when a Diff (Diffusion) pin is connected to an attention-focused wiring segment, a relaxed reference value is used for the verification. In FIG. 14, since the Seg. 3, 1 and Seg. 3, 2 are connected to an output pin (Diffusion pin) of a driver cell, the above relaxed reference value is used for the verification. Conventionally, two methods for correcting an antenna error at a time of layout are available, one being an antenna damage preventing method (1) to be performed by changing wiring topology (wiring layer allocation structure) and an antenna damage preventing method (2) to be performed by connecting a diode.
FIGS. 15A and 15B are diagrams explaining the antenna damage preventing method (1) to be performed by changing the wiring topology. According to the above method (1), as shown in FIG. 15A, a wiring segment which causes an antenna error is first found out (in FIG. 15A, in a state before correction, wiring segment Seg. 2, 1). By employing a placement pattern in which both ends of the wiring segment Seg. 2, 1 causing an error are lifted to an upper layer and a portion except the both ends of the wiring segment Seg. 2, 1 is brought down, and, as shown in FIG. 15B, after the correction, wiring segments Seg. 2, 2, Seg. 3, 1, Seg. 2, 1, Seg. 3, 2 and Seg. 2, 3 are formed. In this case, when the long wiring segment Seg. 2, 1 causing an error was formed, the other segments Seg. 3, 1 and Seg. 3, 2 did not existed. As a result, the Seg. 2, 1 is not connected to the gate pin in a separated manner and, thus, the antenna error is corrected. Owing to this, at the time of plasma etching process, no antenna damage occurs in the gate oxide film of each of the MOS transistors.
FIGS. 16A and 16B are diagrams explaining the antenna damage preventing method (2) to be performed by connecting diodes. According to this method (2), as in the case of the method (1), first, a wiring segment causing an antenna error is found out (before correction, Seg. 2, 1). When its connection state is seen from the Seg. 2, 1, there is no connection of the Seg. 2, 1 to the output pin (Diffusion pin) and, therefore, as a value on the left side of the antenna error judging calculating formula shown in FIG. 14, the reference value not relaxed is used. After the correction, as shown in FIG. 16B, by connecting a diffusion pin being a diode cell to the Seg. 1, 1, as the left side of the judgment calculating formula, a relaxed reference value is used, thus the correction is made.
In addition to the antenna damage preventing methods (1) and (2) described above, another conventional technology of this type is disclosed in Patent Reference 1 (Japanese Patent Application Laid-open No. 2000-114383 [Abstract, FIG. 1]). In the semiconductor integrated circuit interconnection route correcting method disclosed in the Patent Reference 1, one of gates having an amount of estimated damage caused by the erroneous antenna effect which exceeds the maximum permissible amount is selected out and a small area through which the wiring connected to the one of gates and a wiring layer through which the wiring is allowed to pass in the small area are selected and wirings in the small area are peeled off and a correction is made so that the peeled-off wiring passes through the selected wiring layer. If, by this correction, the amount of estimated damage does not become smaller than the maximum permissible amount, the interconnection route is restored to a state existed before the correction of wiring and these processes are repeated until the amount of estimated damage at all gates becomes smaller than the maximum permissible amount.
Still another technology of an automatic wiring-placement apparatus is disclosed in Patent Reference 2 (Japanese Patent Application Laid-open No. 2001-102458 [Page 5, FIG. 2]) in which a wiring in the second layer metal wiring is divided into two wiring portions and a new wiring portion making up the third layer metal wiring is connected between the divided wiring portions.
However, the above antenna damage preventing methods used in the conventional LSI circuit designing system have the following problems. That is, in the antenna damage preventing method (1), as shown in FIGS. 15A and 15B; in a state before correction, the wiring segment Seg. 2, 1 is the segment causing an antenna error and, assuming that the wiring layer M2 serves as the uppermost wiring layer, in a state after correction, the correction and prevention of an antenna damage are impossible by using the further upper wiring layer M3. Therefore, when longer wirings that can be used as signal wirings need to be installed in the uppermost layer, the method (1) cannot be used.
Moreover, in the method (2), as shown in FIG. 17A, in a state before the correction, the wiring segment Seg. 2.1 is the segment causing an antenna error and a diffusion pin is connected to the Seg. 1, 2 of the wiring layer Ml, which brings about a state in which the uppermost layer wiring is connected, all the time, to the diffusion pin of a driver cell and, as a result, a value on the left side of the antenna error judging calculating formula is already a relaxed reference value and, as shown in FIG. 17B illustrating an after-correction state, even if the diffusion pin of the diode cell is further connected to any one of the wiring segments, the correction and prevention are impossible. Thus, by the conventional methods, the problem cannot be solved that wirings on the uppermost layer being able to provide advantages in terms of low-resistance and design for delay are not allowed to be lengthened in an arbitrary manner.
Furthermore, the interconnection route correcting method disclosed in the Patent Reference 1 differs from that of the present invention in that the only purpose of the technology disclosed in the Patent Reference 1 is to change the interconnection route. Also, in the automatic wiring placement apparatus disclosed in the Patent Reference 2, the antenna damage is controlled only by changing interconnection route, which differs from the method of the present invention.